DS3105LN+【PDF 7/124 页】IC TIMING LINE CARD 64-LQFP

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Sheet目录1994

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DS3105

104

JTAG Test Access Port and Boundary Scan

9.1

JTAG Description

The DS3105 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public

instructions included are HIGHZ, CLAMP, and IDCODE. Figure 9-1 shows a block diagram. The DS3105 contains

the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary

Scan Architecture:

Test Access Port (TAP)

Bypass Register

TAP Controller

Boundary Scan Register

Instruction Register

Device Identification Register

The TAP has the necessary interface pins, namely JTCLK,

JTRST, JTDI, JTDO, and JTMS. Details on these pins

can be found in Table 6-5. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.1-

1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.

Figure 9-1. JTAG Block Diagram

BOUNDARY SCAN

DEVICE

IDENTIFICATION

BYPASS REGISTER

INSTRUCTION

TEST ACCESS PORT

CONTROLLER

MUX

SELECT

THREE-STATE

JTDI

50k

JTMS

50k

JTCLK

JTRST

50k

JTDO

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